Load data from unaligned memory corresponding to True elements.
#define vmasko_loadu1(a0, a1, a2, type)
#define vmasko_loadu1_e(a0, a1, a2, type, simd_ext)#define nsimd_masko_loadu1(a0, a1, a2)template <NSIMD_CONCEPT_VALUE_TYPE T> typename simd_traits<T, NSIMD_SIMD>::simd_vector NSIMD_VECTORCALL masko_loadu1(typename simd_traits<T, NSIMD_SIMD>::simd_vectorl a0, T const* a1, typename simd_traits<T, NSIMD_SIMD>::simd_vector a2, T);template <NSIMD_CONCEPT_VALUE_TYPE T, NSIMD_CONCEPT_SIMD_EXT SimdExt> pack<T, 1, SimdExt> masko_loadu1(packl<T, 1, SimdExt> const& a0, T const* a1, pack<T, 1, SimdExt> const& a2);
template <NSIMD_CONCEPT_VALUE_TYPE T, int N, NSIMD_CONCEPT_SIMD_EXT SimdExt> pack<T, N, SimdExt> masko_loadu1(packl<T, N, SimdExt> const& a0, T const* a1, pack<T, N, SimdExt> const& a2);nsimd_avx2_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_f64(nsimd_avx2_vlf64 a0, f64 const* a1, nsimd_avx2_vf64 a2);
nsimd_avx2_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_f32(nsimd_avx2_vlf32 a0, f32 const* a1, nsimd_avx2_vf32 a2);
nsimd_avx2_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_f16(nsimd_avx2_vlf16 a0, f16 const* a1, nsimd_avx2_vf16 a2);
nsimd_avx2_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_i64(nsimd_avx2_vli64 a0, i64 const* a1, nsimd_avx2_vi64 a2);
nsimd_avx2_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_i32(nsimd_avx2_vli32 a0, i32 const* a1, nsimd_avx2_vi32 a2);
nsimd_avx2_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_i16(nsimd_avx2_vli16 a0, i16 const* a1, nsimd_avx2_vi16 a2);
nsimd_avx2_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_i8(nsimd_avx2_vli8 a0, i8 const* a1, nsimd_avx2_vi8 a2);
nsimd_avx2_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_u64(nsimd_avx2_vlu64 a0, u64 const* a1, nsimd_avx2_vu64 a2);
nsimd_avx2_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_u32(nsimd_avx2_vlu32 a0, u32 const* a1, nsimd_avx2_vu32 a2);
nsimd_avx2_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_u16(nsimd_avx2_vlu16 a0, u16 const* a1, nsimd_avx2_vu16 a2);
nsimd_avx2_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx2_u8(nsimd_avx2_vlu8 a0, u8 const* a1, nsimd_avx2_vu8 a2);nsimd_sve512_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_f64(nsimd_sve512_vlf64 a0, f64 const* a1, nsimd_sve512_vf64 a2);
nsimd_sve512_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_f32(nsimd_sve512_vlf32 a0, f32 const* a1, nsimd_sve512_vf32 a2);
nsimd_sve512_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_f16(nsimd_sve512_vlf16 a0, f16 const* a1, nsimd_sve512_vf16 a2);
nsimd_sve512_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_i64(nsimd_sve512_vli64 a0, i64 const* a1, nsimd_sve512_vi64 a2);
nsimd_sve512_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_i32(nsimd_sve512_vli32 a0, i32 const* a1, nsimd_sve512_vi32 a2);
nsimd_sve512_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_i16(nsimd_sve512_vli16 a0, i16 const* a1, nsimd_sve512_vi16 a2);
nsimd_sve512_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_i8(nsimd_sve512_vli8 a0, i8 const* a1, nsimd_sve512_vi8 a2);
nsimd_sve512_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_u64(nsimd_sve512_vlu64 a0, u64 const* a1, nsimd_sve512_vu64 a2);
nsimd_sve512_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_u32(nsimd_sve512_vlu32 a0, u32 const* a1, nsimd_sve512_vu32 a2);
nsimd_sve512_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_u16(nsimd_sve512_vlu16 a0, u16 const* a1, nsimd_sve512_vu16 a2);
nsimd_sve512_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve512_u8(nsimd_sve512_vlu8 a0, u8 const* a1, nsimd_sve512_vu8 a2);nsimd_sve_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_f64(nsimd_sve_vlf64 a0, f64 const* a1, nsimd_sve_vf64 a2);
nsimd_sve_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_f32(nsimd_sve_vlf32 a0, f32 const* a1, nsimd_sve_vf32 a2);
nsimd_sve_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_f16(nsimd_sve_vlf16 a0, f16 const* a1, nsimd_sve_vf16 a2);
nsimd_sve_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_i64(nsimd_sve_vli64 a0, i64 const* a1, nsimd_sve_vi64 a2);
nsimd_sve_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_i32(nsimd_sve_vli32 a0, i32 const* a1, nsimd_sve_vi32 a2);
nsimd_sve_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_i16(nsimd_sve_vli16 a0, i16 const* a1, nsimd_sve_vi16 a2);
nsimd_sve_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_i8(nsimd_sve_vli8 a0, i8 const* a1, nsimd_sve_vi8 a2);
nsimd_sve_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_u64(nsimd_sve_vlu64 a0, u64 const* a1, nsimd_sve_vu64 a2);
nsimd_sve_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_u32(nsimd_sve_vlu32 a0, u32 const* a1, nsimd_sve_vu32 a2);
nsimd_sve_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_u16(nsimd_sve_vlu16 a0, u16 const* a1, nsimd_sve_vu16 a2);
nsimd_sve_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve_u8(nsimd_sve_vlu8 a0, u8 const* a1, nsimd_sve_vu8 a2);nsimd_cpu_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_f64(nsimd_cpu_vlf64 a0, f64 const* a1, nsimd_cpu_vf64 a2);
nsimd_cpu_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_f32(nsimd_cpu_vlf32 a0, f32 const* a1, nsimd_cpu_vf32 a2);
nsimd_cpu_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_f16(nsimd_cpu_vlf16 a0, f16 const* a1, nsimd_cpu_vf16 a2);
nsimd_cpu_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_i64(nsimd_cpu_vli64 a0, i64 const* a1, nsimd_cpu_vi64 a2);
nsimd_cpu_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_i32(nsimd_cpu_vli32 a0, i32 const* a1, nsimd_cpu_vi32 a2);
nsimd_cpu_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_i16(nsimd_cpu_vli16 a0, i16 const* a1, nsimd_cpu_vi16 a2);
nsimd_cpu_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_i8(nsimd_cpu_vli8 a0, i8 const* a1, nsimd_cpu_vi8 a2);
nsimd_cpu_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_u64(nsimd_cpu_vlu64 a0, u64 const* a1, nsimd_cpu_vu64 a2);
nsimd_cpu_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_u32(nsimd_cpu_vlu32 a0, u32 const* a1, nsimd_cpu_vu32 a2);
nsimd_cpu_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_u16(nsimd_cpu_vlu16 a0, u16 const* a1, nsimd_cpu_vu16 a2);
nsimd_cpu_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_cpu_u8(nsimd_cpu_vlu8 a0, u8 const* a1, nsimd_cpu_vu8 a2);nsimd_sve2048_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_f64(nsimd_sve2048_vlf64 a0, f64 const* a1, nsimd_sve2048_vf64 a2);
nsimd_sve2048_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_f32(nsimd_sve2048_vlf32 a0, f32 const* a1, nsimd_sve2048_vf32 a2);
nsimd_sve2048_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_f16(nsimd_sve2048_vlf16 a0, f16 const* a1, nsimd_sve2048_vf16 a2);
nsimd_sve2048_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_i64(nsimd_sve2048_vli64 a0, i64 const* a1, nsimd_sve2048_vi64 a2);
nsimd_sve2048_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_i32(nsimd_sve2048_vli32 a0, i32 const* a1, nsimd_sve2048_vi32 a2);
nsimd_sve2048_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_i16(nsimd_sve2048_vli16 a0, i16 const* a1, nsimd_sve2048_vi16 a2);
nsimd_sve2048_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_i8(nsimd_sve2048_vli8 a0, i8 const* a1, nsimd_sve2048_vi8 a2);
nsimd_sve2048_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_u64(nsimd_sve2048_vlu64 a0, u64 const* a1, nsimd_sve2048_vu64 a2);
nsimd_sve2048_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_u32(nsimd_sve2048_vlu32 a0, u32 const* a1, nsimd_sve2048_vu32 a2);
nsimd_sve2048_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_u16(nsimd_sve2048_vlu16 a0, u16 const* a1, nsimd_sve2048_vu16 a2);
nsimd_sve2048_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve2048_u8(nsimd_sve2048_vlu8 a0, u8 const* a1, nsimd_sve2048_vu8 a2);nsimd_neon128_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_f64(nsimd_neon128_vlf64 a0, f64 const* a1, nsimd_neon128_vf64 a2);
nsimd_neon128_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_f32(nsimd_neon128_vlf32 a0, f32 const* a1, nsimd_neon128_vf32 a2);
nsimd_neon128_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_f16(nsimd_neon128_vlf16 a0, f16 const* a1, nsimd_neon128_vf16 a2);
nsimd_neon128_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_i64(nsimd_neon128_vli64 a0, i64 const* a1, nsimd_neon128_vi64 a2);
nsimd_neon128_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_i32(nsimd_neon128_vli32 a0, i32 const* a1, nsimd_neon128_vi32 a2);
nsimd_neon128_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_i16(nsimd_neon128_vli16 a0, i16 const* a1, nsimd_neon128_vi16 a2);
nsimd_neon128_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_i8(nsimd_neon128_vli8 a0, i8 const* a1, nsimd_neon128_vi8 a2);
nsimd_neon128_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_u64(nsimd_neon128_vlu64 a0, u64 const* a1, nsimd_neon128_vu64 a2);
nsimd_neon128_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_u32(nsimd_neon128_vlu32 a0, u32 const* a1, nsimd_neon128_vu32 a2);
nsimd_neon128_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_u16(nsimd_neon128_vlu16 a0, u16 const* a1, nsimd_neon128_vu16 a2);
nsimd_neon128_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_neon128_u8(nsimd_neon128_vlu8 a0, u8 const* a1, nsimd_neon128_vu8 a2);nsimd_avx512_skylake_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_f64(nsimd_avx512_skylake_vlf64 a0, f64 const* a1, nsimd_avx512_skylake_vf64 a2);
nsimd_avx512_skylake_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_f32(nsimd_avx512_skylake_vlf32 a0, f32 const* a1, nsimd_avx512_skylake_vf32 a2);
nsimd_avx512_skylake_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_f16(nsimd_avx512_skylake_vlf16 a0, f16 const* a1, nsimd_avx512_skylake_vf16 a2);
nsimd_avx512_skylake_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_i64(nsimd_avx512_skylake_vli64 a0, i64 const* a1, nsimd_avx512_skylake_vi64 a2);
nsimd_avx512_skylake_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_i32(nsimd_avx512_skylake_vli32 a0, i32 const* a1, nsimd_avx512_skylake_vi32 a2);
nsimd_avx512_skylake_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_i16(nsimd_avx512_skylake_vli16 a0, i16 const* a1, nsimd_avx512_skylake_vi16 a2);
nsimd_avx512_skylake_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_i8(nsimd_avx512_skylake_vli8 a0, i8 const* a1, nsimd_avx512_skylake_vi8 a2);
nsimd_avx512_skylake_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_u64(nsimd_avx512_skylake_vlu64 a0, u64 const* a1, nsimd_avx512_skylake_vu64 a2);
nsimd_avx512_skylake_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_u32(nsimd_avx512_skylake_vlu32 a0, u32 const* a1, nsimd_avx512_skylake_vu32 a2);
nsimd_avx512_skylake_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_u16(nsimd_avx512_skylake_vlu16 a0, u16 const* a1, nsimd_avx512_skylake_vu16 a2);
nsimd_avx512_skylake_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_skylake_u8(nsimd_avx512_skylake_vlu8 a0, u8 const* a1, nsimd_avx512_skylake_vu8 a2);nsimd_aarch64_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_f64(nsimd_aarch64_vlf64 a0, f64 const* a1, nsimd_aarch64_vf64 a2);
nsimd_aarch64_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_f32(nsimd_aarch64_vlf32 a0, f32 const* a1, nsimd_aarch64_vf32 a2);
nsimd_aarch64_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_f16(nsimd_aarch64_vlf16 a0, f16 const* a1, nsimd_aarch64_vf16 a2);
nsimd_aarch64_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_i64(nsimd_aarch64_vli64 a0, i64 const* a1, nsimd_aarch64_vi64 a2);
nsimd_aarch64_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_i32(nsimd_aarch64_vli32 a0, i32 const* a1, nsimd_aarch64_vi32 a2);
nsimd_aarch64_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_i16(nsimd_aarch64_vli16 a0, i16 const* a1, nsimd_aarch64_vi16 a2);
nsimd_aarch64_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_i8(nsimd_aarch64_vli8 a0, i8 const* a1, nsimd_aarch64_vi8 a2);
nsimd_aarch64_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_u64(nsimd_aarch64_vlu64 a0, u64 const* a1, nsimd_aarch64_vu64 a2);
nsimd_aarch64_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_u32(nsimd_aarch64_vlu32 a0, u32 const* a1, nsimd_aarch64_vu32 a2);
nsimd_aarch64_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_u16(nsimd_aarch64_vlu16 a0, u16 const* a1, nsimd_aarch64_vu16 a2);
nsimd_aarch64_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_aarch64_u8(nsimd_aarch64_vlu8 a0, u8 const* a1, nsimd_aarch64_vu8 a2);nsimd_avx512_knl_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_f64(nsimd_avx512_knl_vlf64 a0, f64 const* a1, nsimd_avx512_knl_vf64 a2);
nsimd_avx512_knl_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_f32(nsimd_avx512_knl_vlf32 a0, f32 const* a1, nsimd_avx512_knl_vf32 a2);
nsimd_avx512_knl_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_f16(nsimd_avx512_knl_vlf16 a0, f16 const* a1, nsimd_avx512_knl_vf16 a2);
nsimd_avx512_knl_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_i64(nsimd_avx512_knl_vli64 a0, i64 const* a1, nsimd_avx512_knl_vi64 a2);
nsimd_avx512_knl_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_i32(nsimd_avx512_knl_vli32 a0, i32 const* a1, nsimd_avx512_knl_vi32 a2);
nsimd_avx512_knl_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_i16(nsimd_avx512_knl_vli16 a0, i16 const* a1, nsimd_avx512_knl_vi16 a2);
nsimd_avx512_knl_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_i8(nsimd_avx512_knl_vli8 a0, i8 const* a1, nsimd_avx512_knl_vi8 a2);
nsimd_avx512_knl_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_u64(nsimd_avx512_knl_vlu64 a0, u64 const* a1, nsimd_avx512_knl_vu64 a2);
nsimd_avx512_knl_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_u32(nsimd_avx512_knl_vlu32 a0, u32 const* a1, nsimd_avx512_knl_vu32 a2);
nsimd_avx512_knl_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_u16(nsimd_avx512_knl_vlu16 a0, u16 const* a1, nsimd_avx512_knl_vu16 a2);
nsimd_avx512_knl_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx512_knl_u8(nsimd_avx512_knl_vlu8 a0, u8 const* a1, nsimd_avx512_knl_vu8 a2);nsimd_sse2_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_f64(nsimd_sse2_vlf64 a0, f64 const* a1, nsimd_sse2_vf64 a2);
nsimd_sse2_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_f32(nsimd_sse2_vlf32 a0, f32 const* a1, nsimd_sse2_vf32 a2);
nsimd_sse2_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_f16(nsimd_sse2_vlf16 a0, f16 const* a1, nsimd_sse2_vf16 a2);
nsimd_sse2_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_i64(nsimd_sse2_vli64 a0, i64 const* a1, nsimd_sse2_vi64 a2);
nsimd_sse2_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_i32(nsimd_sse2_vli32 a0, i32 const* a1, nsimd_sse2_vi32 a2);
nsimd_sse2_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_i16(nsimd_sse2_vli16 a0, i16 const* a1, nsimd_sse2_vi16 a2);
nsimd_sse2_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_i8(nsimd_sse2_vli8 a0, i8 const* a1, nsimd_sse2_vi8 a2);
nsimd_sse2_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_u64(nsimd_sse2_vlu64 a0, u64 const* a1, nsimd_sse2_vu64 a2);
nsimd_sse2_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_u32(nsimd_sse2_vlu32 a0, u32 const* a1, nsimd_sse2_vu32 a2);
nsimd_sse2_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_u16(nsimd_sse2_vlu16 a0, u16 const* a1, nsimd_sse2_vu16 a2);
nsimd_sse2_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sse2_u8(nsimd_sse2_vlu8 a0, u8 const* a1, nsimd_sse2_vu8 a2);nsimd_sse42_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_f64(nsimd_sse42_vlf64 a0, f64 const* a1, nsimd_sse42_vf64 a2);
nsimd_sse42_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_f32(nsimd_sse42_vlf32 a0, f32 const* a1, nsimd_sse42_vf32 a2);
nsimd_sse42_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_f16(nsimd_sse42_vlf16 a0, f16 const* a1, nsimd_sse42_vf16 a2);
nsimd_sse42_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_i64(nsimd_sse42_vli64 a0, i64 const* a1, nsimd_sse42_vi64 a2);
nsimd_sse42_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_i32(nsimd_sse42_vli32 a0, i32 const* a1, nsimd_sse42_vi32 a2);
nsimd_sse42_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_i16(nsimd_sse42_vli16 a0, i16 const* a1, nsimd_sse42_vi16 a2);
nsimd_sse42_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_i8(nsimd_sse42_vli8 a0, i8 const* a1, nsimd_sse42_vi8 a2);
nsimd_sse42_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_u64(nsimd_sse42_vlu64 a0, u64 const* a1, nsimd_sse42_vu64 a2);
nsimd_sse42_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_u32(nsimd_sse42_vlu32 a0, u32 const* a1, nsimd_sse42_vu32 a2);
nsimd_sse42_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_u16(nsimd_sse42_vlu16 a0, u16 const* a1, nsimd_sse42_vu16 a2);
nsimd_sse42_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sse42_u8(nsimd_sse42_vlu8 a0, u8 const* a1, nsimd_sse42_vu8 a2);nsimd_sve256_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_f64(nsimd_sve256_vlf64 a0, f64 const* a1, nsimd_sve256_vf64 a2);
nsimd_sve256_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_f32(nsimd_sve256_vlf32 a0, f32 const* a1, nsimd_sve256_vf32 a2);
nsimd_sve256_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_f16(nsimd_sve256_vlf16 a0, f16 const* a1, nsimd_sve256_vf16 a2);
nsimd_sve256_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_i64(nsimd_sve256_vli64 a0, i64 const* a1, nsimd_sve256_vi64 a2);
nsimd_sve256_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_i32(nsimd_sve256_vli32 a0, i32 const* a1, nsimd_sve256_vi32 a2);
nsimd_sve256_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_i16(nsimd_sve256_vli16 a0, i16 const* a1, nsimd_sve256_vi16 a2);
nsimd_sve256_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_i8(nsimd_sve256_vli8 a0, i8 const* a1, nsimd_sve256_vi8 a2);
nsimd_sve256_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_u64(nsimd_sve256_vlu64 a0, u64 const* a1, nsimd_sve256_vu64 a2);
nsimd_sve256_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_u32(nsimd_sve256_vlu32 a0, u32 const* a1, nsimd_sve256_vu32 a2);
nsimd_sve256_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_u16(nsimd_sve256_vlu16 a0, u16 const* a1, nsimd_sve256_vu16 a2);
nsimd_sve256_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve256_u8(nsimd_sve256_vlu8 a0, u8 const* a1, nsimd_sve256_vu8 a2);nsimd_sve1024_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_f64(nsimd_sve1024_vlf64 a0, f64 const* a1, nsimd_sve1024_vf64 a2);
nsimd_sve1024_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_f32(nsimd_sve1024_vlf32 a0, f32 const* a1, nsimd_sve1024_vf32 a2);
nsimd_sve1024_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_f16(nsimd_sve1024_vlf16 a0, f16 const* a1, nsimd_sve1024_vf16 a2);
nsimd_sve1024_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_i64(nsimd_sve1024_vli64 a0, i64 const* a1, nsimd_sve1024_vi64 a2);
nsimd_sve1024_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_i32(nsimd_sve1024_vli32 a0, i32 const* a1, nsimd_sve1024_vi32 a2);
nsimd_sve1024_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_i16(nsimd_sve1024_vli16 a0, i16 const* a1, nsimd_sve1024_vi16 a2);
nsimd_sve1024_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_i8(nsimd_sve1024_vli8 a0, i8 const* a1, nsimd_sve1024_vi8 a2);
nsimd_sve1024_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_u64(nsimd_sve1024_vlu64 a0, u64 const* a1, nsimd_sve1024_vu64 a2);
nsimd_sve1024_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_u32(nsimd_sve1024_vlu32 a0, u32 const* a1, nsimd_sve1024_vu32 a2);
nsimd_sve1024_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_u16(nsimd_sve1024_vlu16 a0, u16 const* a1, nsimd_sve1024_vu16 a2);
nsimd_sve1024_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve1024_u8(nsimd_sve1024_vlu8 a0, u8 const* a1, nsimd_sve1024_vu8 a2);nsimd_vsx_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_f64(nsimd_vsx_vlf64 a0, f64 const* a1, nsimd_vsx_vf64 a2);
nsimd_vsx_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_f32(nsimd_vsx_vlf32 a0, f32 const* a1, nsimd_vsx_vf32 a2);
nsimd_vsx_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_f16(nsimd_vsx_vlf16 a0, f16 const* a1, nsimd_vsx_vf16 a2);
nsimd_vsx_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_i64(nsimd_vsx_vli64 a0, i64 const* a1, nsimd_vsx_vi64 a2);
nsimd_vsx_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_i32(nsimd_vsx_vli32 a0, i32 const* a1, nsimd_vsx_vi32 a2);
nsimd_vsx_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_i16(nsimd_vsx_vli16 a0, i16 const* a1, nsimd_vsx_vi16 a2);
nsimd_vsx_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_i8(nsimd_vsx_vli8 a0, i8 const* a1, nsimd_vsx_vi8 a2);
nsimd_vsx_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_u64(nsimd_vsx_vlu64 a0, u64 const* a1, nsimd_vsx_vu64 a2);
nsimd_vsx_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_u32(nsimd_vsx_vlu32 a0, u32 const* a1, nsimd_vsx_vu32 a2);
nsimd_vsx_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_u16(nsimd_vsx_vlu16 a0, u16 const* a1, nsimd_vsx_vu16 a2);
nsimd_vsx_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_vsx_u8(nsimd_vsx_vlu8 a0, u8 const* a1, nsimd_vsx_vu8 a2);nsimd_sve128_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_f64(nsimd_sve128_vlf64 a0, f64 const* a1, nsimd_sve128_vf64 a2);
nsimd_sve128_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_f32(nsimd_sve128_vlf32 a0, f32 const* a1, nsimd_sve128_vf32 a2);
nsimd_sve128_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_f16(nsimd_sve128_vlf16 a0, f16 const* a1, nsimd_sve128_vf16 a2);
nsimd_sve128_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_i64(nsimd_sve128_vli64 a0, i64 const* a1, nsimd_sve128_vi64 a2);
nsimd_sve128_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_i32(nsimd_sve128_vli32 a0, i32 const* a1, nsimd_sve128_vi32 a2);
nsimd_sve128_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_i16(nsimd_sve128_vli16 a0, i16 const* a1, nsimd_sve128_vi16 a2);
nsimd_sve128_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_i8(nsimd_sve128_vli8 a0, i8 const* a1, nsimd_sve128_vi8 a2);
nsimd_sve128_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_u64(nsimd_sve128_vlu64 a0, u64 const* a1, nsimd_sve128_vu64 a2);
nsimd_sve128_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_u32(nsimd_sve128_vlu32 a0, u32 const* a1, nsimd_sve128_vu32 a2);
nsimd_sve128_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_u16(nsimd_sve128_vlu16 a0, u16 const* a1, nsimd_sve128_vu16 a2);
nsimd_sve128_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_sve128_u8(nsimd_sve128_vlu8 a0, u8 const* a1, nsimd_sve128_vu8 a2);nsimd_vmx_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_f64(nsimd_vmx_vlf64 a0, f64 const* a1, nsimd_vmx_vf64 a2);
nsimd_vmx_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_f32(nsimd_vmx_vlf32 a0, f32 const* a1, nsimd_vmx_vf32 a2);
nsimd_vmx_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_f16(nsimd_vmx_vlf16 a0, f16 const* a1, nsimd_vmx_vf16 a2);
nsimd_vmx_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_i64(nsimd_vmx_vli64 a0, i64 const* a1, nsimd_vmx_vi64 a2);
nsimd_vmx_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_i32(nsimd_vmx_vli32 a0, i32 const* a1, nsimd_vmx_vi32 a2);
nsimd_vmx_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_i16(nsimd_vmx_vli16 a0, i16 const* a1, nsimd_vmx_vi16 a2);
nsimd_vmx_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_i8(nsimd_vmx_vli8 a0, i8 const* a1, nsimd_vmx_vi8 a2);
nsimd_vmx_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_u64(nsimd_vmx_vlu64 a0, u64 const* a1, nsimd_vmx_vu64 a2);
nsimd_vmx_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_u32(nsimd_vmx_vlu32 a0, u32 const* a1, nsimd_vmx_vu32 a2);
nsimd_vmx_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_u16(nsimd_vmx_vlu16 a0, u16 const* a1, nsimd_vmx_vu16 a2);
nsimd_vmx_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_vmx_u8(nsimd_vmx_vlu8 a0, u8 const* a1, nsimd_vmx_vu8 a2);nsimd_avx_vf64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_f64(nsimd_avx_vlf64 a0, f64 const* a1, nsimd_avx_vf64 a2);
nsimd_avx_vf32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_f32(nsimd_avx_vlf32 a0, f32 const* a1, nsimd_avx_vf32 a2);
nsimd_avx_vf16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_f16(nsimd_avx_vlf16 a0, f16 const* a1, nsimd_avx_vf16 a2);
nsimd_avx_vi64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_i64(nsimd_avx_vli64 a0, i64 const* a1, nsimd_avx_vi64 a2);
nsimd_avx_vi32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_i32(nsimd_avx_vli32 a0, i32 const* a1, nsimd_avx_vi32 a2);
nsimd_avx_vi16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_i16(nsimd_avx_vli16 a0, i16 const* a1, nsimd_avx_vi16 a2);
nsimd_avx_vi8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_i8(nsimd_avx_vli8 a0, i8 const* a1, nsimd_avx_vi8 a2);
nsimd_avx_vu64 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_u64(nsimd_avx_vlu64 a0, u64 const* a1, nsimd_avx_vu64 a2);
nsimd_avx_vu32 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_u32(nsimd_avx_vlu32 a0, u32 const* a1, nsimd_avx_vu32 a2);
nsimd_avx_vu16 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_u16(nsimd_avx_vlu16 a0, u16 const* a1, nsimd_avx_vu16 a2);
nsimd_avx_vu8 NSIMD_VECTORCALL nsimd_masko_loadu1_avx_u8(nsimd_avx_vlu8 a0, u8 const* a1, nsimd_avx_vu8 a2);nsimd_avx2_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlf64 a0, f64 const* a1, nsimd_avx2_vf64 a2, f64, avx2);
nsimd_avx2_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlf32 a0, f32 const* a1, nsimd_avx2_vf32 a2, f32, avx2);
nsimd_avx2_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlf16 a0, f16 const* a1, nsimd_avx2_vf16 a2, f16, avx2);
nsimd_avx2_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vli64 a0, i64 const* a1, nsimd_avx2_vi64 a2, i64, avx2);
nsimd_avx2_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vli32 a0, i32 const* a1, nsimd_avx2_vi32 a2, i32, avx2);
nsimd_avx2_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vli16 a0, i16 const* a1, nsimd_avx2_vi16 a2, i16, avx2);
nsimd_avx2_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vli8 a0, i8 const* a1, nsimd_avx2_vi8 a2, i8, avx2);
nsimd_avx2_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlu64 a0, u64 const* a1, nsimd_avx2_vu64 a2, u64, avx2);
nsimd_avx2_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlu32 a0, u32 const* a1, nsimd_avx2_vu32 a2, u32, avx2);
nsimd_avx2_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlu16 a0, u16 const* a1, nsimd_avx2_vu16 a2, u16, avx2);
nsimd_avx2_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx2_vlu8 a0, u8 const* a1, nsimd_avx2_vu8 a2, u8, avx2);nsimd_sve512_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlf64 a0, f64 const* a1, nsimd_sve512_vf64 a2, f64, sve512);
nsimd_sve512_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlf32 a0, f32 const* a1, nsimd_sve512_vf32 a2, f32, sve512);
nsimd_sve512_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlf16 a0, f16 const* a1, nsimd_sve512_vf16 a2, f16, sve512);
nsimd_sve512_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vli64 a0, i64 const* a1, nsimd_sve512_vi64 a2, i64, sve512);
nsimd_sve512_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vli32 a0, i32 const* a1, nsimd_sve512_vi32 a2, i32, sve512);
nsimd_sve512_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vli16 a0, i16 const* a1, nsimd_sve512_vi16 a2, i16, sve512);
nsimd_sve512_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vli8 a0, i8 const* a1, nsimd_sve512_vi8 a2, i8, sve512);
nsimd_sve512_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlu64 a0, u64 const* a1, nsimd_sve512_vu64 a2, u64, sve512);
nsimd_sve512_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlu32 a0, u32 const* a1, nsimd_sve512_vu32 a2, u32, sve512);
nsimd_sve512_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlu16 a0, u16 const* a1, nsimd_sve512_vu16 a2, u16, sve512);
nsimd_sve512_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve512_vlu8 a0, u8 const* a1, nsimd_sve512_vu8 a2, u8, sve512);nsimd_sve_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlf64 a0, f64 const* a1, nsimd_sve_vf64 a2, f64, sve);
nsimd_sve_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlf32 a0, f32 const* a1, nsimd_sve_vf32 a2, f32, sve);
nsimd_sve_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlf16 a0, f16 const* a1, nsimd_sve_vf16 a2, f16, sve);
nsimd_sve_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vli64 a0, i64 const* a1, nsimd_sve_vi64 a2, i64, sve);
nsimd_sve_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vli32 a0, i32 const* a1, nsimd_sve_vi32 a2, i32, sve);
nsimd_sve_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vli16 a0, i16 const* a1, nsimd_sve_vi16 a2, i16, sve);
nsimd_sve_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vli8 a0, i8 const* a1, nsimd_sve_vi8 a2, i8, sve);
nsimd_sve_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlu64 a0, u64 const* a1, nsimd_sve_vu64 a2, u64, sve);
nsimd_sve_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlu32 a0, u32 const* a1, nsimd_sve_vu32 a2, u32, sve);
nsimd_sve_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlu16 a0, u16 const* a1, nsimd_sve_vu16 a2, u16, sve);
nsimd_sve_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve_vlu8 a0, u8 const* a1, nsimd_sve_vu8 a2, u8, sve);nsimd_cpu_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlf64 a0, f64 const* a1, nsimd_cpu_vf64 a2, f64, cpu);
nsimd_cpu_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlf32 a0, f32 const* a1, nsimd_cpu_vf32 a2, f32, cpu);
nsimd_cpu_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlf16 a0, f16 const* a1, nsimd_cpu_vf16 a2, f16, cpu);
nsimd_cpu_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vli64 a0, i64 const* a1, nsimd_cpu_vi64 a2, i64, cpu);
nsimd_cpu_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vli32 a0, i32 const* a1, nsimd_cpu_vi32 a2, i32, cpu);
nsimd_cpu_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vli16 a0, i16 const* a1, nsimd_cpu_vi16 a2, i16, cpu);
nsimd_cpu_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vli8 a0, i8 const* a1, nsimd_cpu_vi8 a2, i8, cpu);
nsimd_cpu_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlu64 a0, u64 const* a1, nsimd_cpu_vu64 a2, u64, cpu);
nsimd_cpu_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlu32 a0, u32 const* a1, nsimd_cpu_vu32 a2, u32, cpu);
nsimd_cpu_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlu16 a0, u16 const* a1, nsimd_cpu_vu16 a2, u16, cpu);
nsimd_cpu_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_cpu_vlu8 a0, u8 const* a1, nsimd_cpu_vu8 a2, u8, cpu);nsimd_sve2048_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlf64 a0, f64 const* a1, nsimd_sve2048_vf64 a2, f64, sve2048);
nsimd_sve2048_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlf32 a0, f32 const* a1, nsimd_sve2048_vf32 a2, f32, sve2048);
nsimd_sve2048_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlf16 a0, f16 const* a1, nsimd_sve2048_vf16 a2, f16, sve2048);
nsimd_sve2048_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vli64 a0, i64 const* a1, nsimd_sve2048_vi64 a2, i64, sve2048);
nsimd_sve2048_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vli32 a0, i32 const* a1, nsimd_sve2048_vi32 a2, i32, sve2048);
nsimd_sve2048_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vli16 a0, i16 const* a1, nsimd_sve2048_vi16 a2, i16, sve2048);
nsimd_sve2048_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vli8 a0, i8 const* a1, nsimd_sve2048_vi8 a2, i8, sve2048);
nsimd_sve2048_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlu64 a0, u64 const* a1, nsimd_sve2048_vu64 a2, u64, sve2048);
nsimd_sve2048_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlu32 a0, u32 const* a1, nsimd_sve2048_vu32 a2, u32, sve2048);
nsimd_sve2048_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlu16 a0, u16 const* a1, nsimd_sve2048_vu16 a2, u16, sve2048);
nsimd_sve2048_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve2048_vlu8 a0, u8 const* a1, nsimd_sve2048_vu8 a2, u8, sve2048);nsimd_neon128_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlf64 a0, f64 const* a1, nsimd_neon128_vf64 a2, f64, neon128);
nsimd_neon128_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlf32 a0, f32 const* a1, nsimd_neon128_vf32 a2, f32, neon128);
nsimd_neon128_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlf16 a0, f16 const* a1, nsimd_neon128_vf16 a2, f16, neon128);
nsimd_neon128_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vli64 a0, i64 const* a1, nsimd_neon128_vi64 a2, i64, neon128);
nsimd_neon128_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vli32 a0, i32 const* a1, nsimd_neon128_vi32 a2, i32, neon128);
nsimd_neon128_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vli16 a0, i16 const* a1, nsimd_neon128_vi16 a2, i16, neon128);
nsimd_neon128_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vli8 a0, i8 const* a1, nsimd_neon128_vi8 a2, i8, neon128);
nsimd_neon128_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlu64 a0, u64 const* a1, nsimd_neon128_vu64 a2, u64, neon128);
nsimd_neon128_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlu32 a0, u32 const* a1, nsimd_neon128_vu32 a2, u32, neon128);
nsimd_neon128_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlu16 a0, u16 const* a1, nsimd_neon128_vu16 a2, u16, neon128);
nsimd_neon128_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_neon128_vlu8 a0, u8 const* a1, nsimd_neon128_vu8 a2, u8, neon128);nsimd_avx512_skylake_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlf64 a0, f64 const* a1, nsimd_avx512_skylake_vf64 a2, f64, avx512_skylake);
nsimd_avx512_skylake_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlf32 a0, f32 const* a1, nsimd_avx512_skylake_vf32 a2, f32, avx512_skylake);
nsimd_avx512_skylake_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlf16 a0, f16 const* a1, nsimd_avx512_skylake_vf16 a2, f16, avx512_skylake);
nsimd_avx512_skylake_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vli64 a0, i64 const* a1, nsimd_avx512_skylake_vi64 a2, i64, avx512_skylake);
nsimd_avx512_skylake_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vli32 a0, i32 const* a1, nsimd_avx512_skylake_vi32 a2, i32, avx512_skylake);
nsimd_avx512_skylake_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vli16 a0, i16 const* a1, nsimd_avx512_skylake_vi16 a2, i16, avx512_skylake);
nsimd_avx512_skylake_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vli8 a0, i8 const* a1, nsimd_avx512_skylake_vi8 a2, i8, avx512_skylake);
nsimd_avx512_skylake_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlu64 a0, u64 const* a1, nsimd_avx512_skylake_vu64 a2, u64, avx512_skylake);
nsimd_avx512_skylake_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlu32 a0, u32 const* a1, nsimd_avx512_skylake_vu32 a2, u32, avx512_skylake);
nsimd_avx512_skylake_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlu16 a0, u16 const* a1, nsimd_avx512_skylake_vu16 a2, u16, avx512_skylake);
nsimd_avx512_skylake_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_skylake_vlu8 a0, u8 const* a1, nsimd_avx512_skylake_vu8 a2, u8, avx512_skylake);nsimd_aarch64_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlf64 a0, f64 const* a1, nsimd_aarch64_vf64 a2, f64, aarch64);
nsimd_aarch64_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlf32 a0, f32 const* a1, nsimd_aarch64_vf32 a2, f32, aarch64);
nsimd_aarch64_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlf16 a0, f16 const* a1, nsimd_aarch64_vf16 a2, f16, aarch64);
nsimd_aarch64_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vli64 a0, i64 const* a1, nsimd_aarch64_vi64 a2, i64, aarch64);
nsimd_aarch64_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vli32 a0, i32 const* a1, nsimd_aarch64_vi32 a2, i32, aarch64);
nsimd_aarch64_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vli16 a0, i16 const* a1, nsimd_aarch64_vi16 a2, i16, aarch64);
nsimd_aarch64_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vli8 a0, i8 const* a1, nsimd_aarch64_vi8 a2, i8, aarch64);
nsimd_aarch64_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlu64 a0, u64 const* a1, nsimd_aarch64_vu64 a2, u64, aarch64);
nsimd_aarch64_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlu32 a0, u32 const* a1, nsimd_aarch64_vu32 a2, u32, aarch64);
nsimd_aarch64_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlu16 a0, u16 const* a1, nsimd_aarch64_vu16 a2, u16, aarch64);
nsimd_aarch64_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_aarch64_vlu8 a0, u8 const* a1, nsimd_aarch64_vu8 a2, u8, aarch64);nsimd_avx512_knl_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlf64 a0, f64 const* a1, nsimd_avx512_knl_vf64 a2, f64, avx512_knl);
nsimd_avx512_knl_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlf32 a0, f32 const* a1, nsimd_avx512_knl_vf32 a2, f32, avx512_knl);
nsimd_avx512_knl_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlf16 a0, f16 const* a1, nsimd_avx512_knl_vf16 a2, f16, avx512_knl);
nsimd_avx512_knl_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vli64 a0, i64 const* a1, nsimd_avx512_knl_vi64 a2, i64, avx512_knl);
nsimd_avx512_knl_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vli32 a0, i32 const* a1, nsimd_avx512_knl_vi32 a2, i32, avx512_knl);
nsimd_avx512_knl_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vli16 a0, i16 const* a1, nsimd_avx512_knl_vi16 a2, i16, avx512_knl);
nsimd_avx512_knl_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vli8 a0, i8 const* a1, nsimd_avx512_knl_vi8 a2, i8, avx512_knl);
nsimd_avx512_knl_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlu64 a0, u64 const* a1, nsimd_avx512_knl_vu64 a2, u64, avx512_knl);
nsimd_avx512_knl_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlu32 a0, u32 const* a1, nsimd_avx512_knl_vu32 a2, u32, avx512_knl);
nsimd_avx512_knl_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlu16 a0, u16 const* a1, nsimd_avx512_knl_vu16 a2, u16, avx512_knl);
nsimd_avx512_knl_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx512_knl_vlu8 a0, u8 const* a1, nsimd_avx512_knl_vu8 a2, u8, avx512_knl);nsimd_sse2_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlf64 a0, f64 const* a1, nsimd_sse2_vf64 a2, f64, sse2);
nsimd_sse2_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlf32 a0, f32 const* a1, nsimd_sse2_vf32 a2, f32, sse2);
nsimd_sse2_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlf16 a0, f16 const* a1, nsimd_sse2_vf16 a2, f16, sse2);
nsimd_sse2_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vli64 a0, i64 const* a1, nsimd_sse2_vi64 a2, i64, sse2);
nsimd_sse2_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vli32 a0, i32 const* a1, nsimd_sse2_vi32 a2, i32, sse2);
nsimd_sse2_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vli16 a0, i16 const* a1, nsimd_sse2_vi16 a2, i16, sse2);
nsimd_sse2_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vli8 a0, i8 const* a1, nsimd_sse2_vi8 a2, i8, sse2);
nsimd_sse2_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlu64 a0, u64 const* a1, nsimd_sse2_vu64 a2, u64, sse2);
nsimd_sse2_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlu32 a0, u32 const* a1, nsimd_sse2_vu32 a2, u32, sse2);
nsimd_sse2_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlu16 a0, u16 const* a1, nsimd_sse2_vu16 a2, u16, sse2);
nsimd_sse2_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sse2_vlu8 a0, u8 const* a1, nsimd_sse2_vu8 a2, u8, sse2);nsimd_sse42_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlf64 a0, f64 const* a1, nsimd_sse42_vf64 a2, f64, sse42);
nsimd_sse42_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlf32 a0, f32 const* a1, nsimd_sse42_vf32 a2, f32, sse42);
nsimd_sse42_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlf16 a0, f16 const* a1, nsimd_sse42_vf16 a2, f16, sse42);
nsimd_sse42_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vli64 a0, i64 const* a1, nsimd_sse42_vi64 a2, i64, sse42);
nsimd_sse42_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vli32 a0, i32 const* a1, nsimd_sse42_vi32 a2, i32, sse42);
nsimd_sse42_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vli16 a0, i16 const* a1, nsimd_sse42_vi16 a2, i16, sse42);
nsimd_sse42_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vli8 a0, i8 const* a1, nsimd_sse42_vi8 a2, i8, sse42);
nsimd_sse42_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlu64 a0, u64 const* a1, nsimd_sse42_vu64 a2, u64, sse42);
nsimd_sse42_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlu32 a0, u32 const* a1, nsimd_sse42_vu32 a2, u32, sse42);
nsimd_sse42_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlu16 a0, u16 const* a1, nsimd_sse42_vu16 a2, u16, sse42);
nsimd_sse42_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sse42_vlu8 a0, u8 const* a1, nsimd_sse42_vu8 a2, u8, sse42);nsimd_sve256_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlf64 a0, f64 const* a1, nsimd_sve256_vf64 a2, f64, sve256);
nsimd_sve256_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlf32 a0, f32 const* a1, nsimd_sve256_vf32 a2, f32, sve256);
nsimd_sve256_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlf16 a0, f16 const* a1, nsimd_sve256_vf16 a2, f16, sve256);
nsimd_sve256_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vli64 a0, i64 const* a1, nsimd_sve256_vi64 a2, i64, sve256);
nsimd_sve256_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vli32 a0, i32 const* a1, nsimd_sve256_vi32 a2, i32, sve256);
nsimd_sve256_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vli16 a0, i16 const* a1, nsimd_sve256_vi16 a2, i16, sve256);
nsimd_sve256_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vli8 a0, i8 const* a1, nsimd_sve256_vi8 a2, i8, sve256);
nsimd_sve256_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlu64 a0, u64 const* a1, nsimd_sve256_vu64 a2, u64, sve256);
nsimd_sve256_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlu32 a0, u32 const* a1, nsimd_sve256_vu32 a2, u32, sve256);
nsimd_sve256_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlu16 a0, u16 const* a1, nsimd_sve256_vu16 a2, u16, sve256);
nsimd_sve256_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve256_vlu8 a0, u8 const* a1, nsimd_sve256_vu8 a2, u8, sve256);nsimd_sve1024_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlf64 a0, f64 const* a1, nsimd_sve1024_vf64 a2, f64, sve1024);
nsimd_sve1024_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlf32 a0, f32 const* a1, nsimd_sve1024_vf32 a2, f32, sve1024);
nsimd_sve1024_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlf16 a0, f16 const* a1, nsimd_sve1024_vf16 a2, f16, sve1024);
nsimd_sve1024_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vli64 a0, i64 const* a1, nsimd_sve1024_vi64 a2, i64, sve1024);
nsimd_sve1024_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vli32 a0, i32 const* a1, nsimd_sve1024_vi32 a2, i32, sve1024);
nsimd_sve1024_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vli16 a0, i16 const* a1, nsimd_sve1024_vi16 a2, i16, sve1024);
nsimd_sve1024_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vli8 a0, i8 const* a1, nsimd_sve1024_vi8 a2, i8, sve1024);
nsimd_sve1024_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlu64 a0, u64 const* a1, nsimd_sve1024_vu64 a2, u64, sve1024);
nsimd_sve1024_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlu32 a0, u32 const* a1, nsimd_sve1024_vu32 a2, u32, sve1024);
nsimd_sve1024_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlu16 a0, u16 const* a1, nsimd_sve1024_vu16 a2, u16, sve1024);
nsimd_sve1024_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve1024_vlu8 a0, u8 const* a1, nsimd_sve1024_vu8 a2, u8, sve1024);nsimd_vsx_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlf64 a0, f64 const* a1, nsimd_vsx_vf64 a2, f64, vsx);
nsimd_vsx_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlf32 a0, f32 const* a1, nsimd_vsx_vf32 a2, f32, vsx);
nsimd_vsx_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlf16 a0, f16 const* a1, nsimd_vsx_vf16 a2, f16, vsx);
nsimd_vsx_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vli64 a0, i64 const* a1, nsimd_vsx_vi64 a2, i64, vsx);
nsimd_vsx_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vli32 a0, i32 const* a1, nsimd_vsx_vi32 a2, i32, vsx);
nsimd_vsx_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vli16 a0, i16 const* a1, nsimd_vsx_vi16 a2, i16, vsx);
nsimd_vsx_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vli8 a0, i8 const* a1, nsimd_vsx_vi8 a2, i8, vsx);
nsimd_vsx_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlu64 a0, u64 const* a1, nsimd_vsx_vu64 a2, u64, vsx);
nsimd_vsx_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlu32 a0, u32 const* a1, nsimd_vsx_vu32 a2, u32, vsx);
nsimd_vsx_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlu16 a0, u16 const* a1, nsimd_vsx_vu16 a2, u16, vsx);
nsimd_vsx_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_vsx_vlu8 a0, u8 const* a1, nsimd_vsx_vu8 a2, u8, vsx);nsimd_sve128_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlf64 a0, f64 const* a1, nsimd_sve128_vf64 a2, f64, sve128);
nsimd_sve128_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlf32 a0, f32 const* a1, nsimd_sve128_vf32 a2, f32, sve128);
nsimd_sve128_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlf16 a0, f16 const* a1, nsimd_sve128_vf16 a2, f16, sve128);
nsimd_sve128_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vli64 a0, i64 const* a1, nsimd_sve128_vi64 a2, i64, sve128);
nsimd_sve128_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vli32 a0, i32 const* a1, nsimd_sve128_vi32 a2, i32, sve128);
nsimd_sve128_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vli16 a0, i16 const* a1, nsimd_sve128_vi16 a2, i16, sve128);
nsimd_sve128_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vli8 a0, i8 const* a1, nsimd_sve128_vi8 a2, i8, sve128);
nsimd_sve128_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlu64 a0, u64 const* a1, nsimd_sve128_vu64 a2, u64, sve128);
nsimd_sve128_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlu32 a0, u32 const* a1, nsimd_sve128_vu32 a2, u32, sve128);
nsimd_sve128_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlu16 a0, u16 const* a1, nsimd_sve128_vu16 a2, u16, sve128);
nsimd_sve128_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_sve128_vlu8 a0, u8 const* a1, nsimd_sve128_vu8 a2, u8, sve128);nsimd_vmx_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlf64 a0, f64 const* a1, nsimd_vmx_vf64 a2, f64, vmx);
nsimd_vmx_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlf32 a0, f32 const* a1, nsimd_vmx_vf32 a2, f32, vmx);
nsimd_vmx_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlf16 a0, f16 const* a1, nsimd_vmx_vf16 a2, f16, vmx);
nsimd_vmx_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vli64 a0, i64 const* a1, nsimd_vmx_vi64 a2, i64, vmx);
nsimd_vmx_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vli32 a0, i32 const* a1, nsimd_vmx_vi32 a2, i32, vmx);
nsimd_vmx_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vli16 a0, i16 const* a1, nsimd_vmx_vi16 a2, i16, vmx);
nsimd_vmx_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vli8 a0, i8 const* a1, nsimd_vmx_vi8 a2, i8, vmx);
nsimd_vmx_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlu64 a0, u64 const* a1, nsimd_vmx_vu64 a2, u64, vmx);
nsimd_vmx_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlu32 a0, u32 const* a1, nsimd_vmx_vu32 a2, u32, vmx);
nsimd_vmx_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlu16 a0, u16 const* a1, nsimd_vmx_vu16 a2, u16, vmx);
nsimd_vmx_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_vmx_vlu8 a0, u8 const* a1, nsimd_vmx_vu8 a2, u8, vmx);nsimd_avx_vf64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlf64 a0, f64 const* a1, nsimd_avx_vf64 a2, f64, avx);
nsimd_avx_vf32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlf32 a0, f32 const* a1, nsimd_avx_vf32 a2, f32, avx);
nsimd_avx_vf16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlf16 a0, f16 const* a1, nsimd_avx_vf16 a2, f16, avx);
nsimd_avx_vi64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vli64 a0, i64 const* a1, nsimd_avx_vi64 a2, i64, avx);
nsimd_avx_vi32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vli32 a0, i32 const* a1, nsimd_avx_vi32 a2, i32, avx);
nsimd_avx_vi16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vli16 a0, i16 const* a1, nsimd_avx_vi16 a2, i16, avx);
nsimd_avx_vi8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vli8 a0, i8 const* a1, nsimd_avx_vi8 a2, i8, avx);
nsimd_avx_vu64 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlu64 a0, u64 const* a1, nsimd_avx_vu64 a2, u64, avx);
nsimd_avx_vu32 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlu32 a0, u32 const* a1, nsimd_avx_vu32 a2, u32, avx);
nsimd_avx_vu16 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlu16 a0, u16 const* a1, nsimd_avx_vu16 a2, u16, avx);
nsimd_avx_vu8 NSIMD_VECTORCALL masko_loadu1(nsimd_avx_vlu8 a0, u8 const* a1, nsimd_avx_vu8 a2, u8, avx);