Convert input vector into a different larger vector type. The output type must be twice as large as the input type.
#define vupcvt(a0, from_type, to_type)
#define vupcvt_e(a0, from_type, to_type, simd_ext)#define nsimd_upcvt(to_type, a0)template <NSIMD_CONCEPT_VALUE_TYPE F, NSIMD_CONCEPT_VALUE_TYPE T> NSIMD_REQUIRES(2 * sizeof_v<F> == sizeof_v<T>) typename simd_traits<T, NSIMD_SIMD>::simd_vectorx2 NSIMD_VECTORCALL upcvt(typename simd_traits<F, NSIMD_SIMD>::simd_vector a0, F, T);template <NSIMD_CONCEPT_PACKX2 ToPackType, NSIMD_CONCEPT_VALUE_TYPE T, NSIMD_CONCEPT_SIMD_EXT SimdExt> NSIMD_REQUIRES((sizeof_v<typename ToPackType::value_type> == 2 * sizeof_v<T> && ToPackType::unroll == 1 && std::is_same_v<typename ToPackType::simd_ext, SimdExt>))ToPackType upcvt(ToPackType const&, pack<T, 1, SimdExt> const& a0);
template <NSIMD_CONCEPT_PACKX2 ToPackType, NSIMD_CONCEPT_VALUE_TYPE T, int N, NSIMD_CONCEPT_SIMD_EXT SimdExt> NSIMD_REQUIRES((sizeof_v<typename ToPackType::value_type> == 2 * sizeof_v<T> && ToPackType::unroll == N && std::is_same_v<typename ToPackType::simd_ext, SimdExt>))ToPackType upcvt(ToPackType const&, pack<T, N, SimdExt> const& a0);
template <NSIMD_CONCEPT_PACKX2 ToPackType, NSIMD_CONCEPT_VALUE_TYPE T, int N, NSIMD_CONCEPT_SIMD_EXT SimdExt> NSIMD_REQUIRES((sizeof_v<typename ToPackType::value_type> == 2 * sizeof_v<T> && ToPackType::unroll == N && std::is_same_v<typename ToPackType::simd_ext, SimdExt>))ToPackType upcvt(pack<T, N, SimdExt> const& a0);nsimd_avx2_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_i8_i8(nsimd_avx2_vi8 a0);
nsimd_avx2_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_u8_u8(nsimd_avx2_vu8 a0);
nsimd_avx2_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_i16_i16(nsimd_avx2_vi16 a0);
nsimd_avx2_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_u16_u16(nsimd_avx2_vu16 a0);
nsimd_avx2_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_f16_f16(nsimd_avx2_vf16 a0);
nsimd_avx2_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_i32_i32(nsimd_avx2_vi32 a0);
nsimd_avx2_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_u32_u32(nsimd_avx2_vu32 a0);
nsimd_avx2_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_avx2_f32_f32(nsimd_avx2_vf32 a0);nsimd_sve512_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_i8_i8(nsimd_sve512_vi8 a0);
nsimd_sve512_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_u8_u8(nsimd_sve512_vu8 a0);
nsimd_sve512_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_i16_i16(nsimd_sve512_vi16 a0);
nsimd_sve512_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_u16_u16(nsimd_sve512_vu16 a0);
nsimd_sve512_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_f16_f16(nsimd_sve512_vf16 a0);
nsimd_sve512_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_i32_i32(nsimd_sve512_vi32 a0);
nsimd_sve512_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_u32_u32(nsimd_sve512_vu32 a0);
nsimd_sve512_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve512_f32_f32(nsimd_sve512_vf32 a0);nsimd_sve_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve_i8_i8(nsimd_sve_vi8 a0);
nsimd_sve_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve_u8_u8(nsimd_sve_vu8 a0);
nsimd_sve_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve_i16_i16(nsimd_sve_vi16 a0);
nsimd_sve_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve_u16_u16(nsimd_sve_vu16 a0);
nsimd_sve_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve_f16_f16(nsimd_sve_vf16 a0);
nsimd_sve_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve_i32_i32(nsimd_sve_vi32 a0);
nsimd_sve_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve_u32_u32(nsimd_sve_vu32 a0);
nsimd_sve_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve_f32_f32(nsimd_sve_vf32 a0);nsimd_cpu_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_i8_i8(nsimd_cpu_vi8 a0);
nsimd_cpu_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_u8_u8(nsimd_cpu_vu8 a0);
nsimd_cpu_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_i16_i16(nsimd_cpu_vi16 a0);
nsimd_cpu_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_u16_u16(nsimd_cpu_vu16 a0);
nsimd_cpu_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_f16_f16(nsimd_cpu_vf16 a0);
nsimd_cpu_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_i32_i32(nsimd_cpu_vi32 a0);
nsimd_cpu_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_u32_u32(nsimd_cpu_vu32 a0);
nsimd_cpu_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_cpu_f32_f32(nsimd_cpu_vf32 a0);nsimd_sve2048_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_i8_i8(nsimd_sve2048_vi8 a0);
nsimd_sve2048_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_u8_u8(nsimd_sve2048_vu8 a0);
nsimd_sve2048_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_i16_i16(nsimd_sve2048_vi16 a0);
nsimd_sve2048_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_u16_u16(nsimd_sve2048_vu16 a0);
nsimd_sve2048_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_f16_f16(nsimd_sve2048_vf16 a0);
nsimd_sve2048_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_i32_i32(nsimd_sve2048_vi32 a0);
nsimd_sve2048_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_u32_u32(nsimd_sve2048_vu32 a0);
nsimd_sve2048_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve2048_f32_f32(nsimd_sve2048_vf32 a0);nsimd_neon128_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_i8_i8(nsimd_neon128_vi8 a0);
nsimd_neon128_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_u8_u8(nsimd_neon128_vu8 a0);
nsimd_neon128_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_i16_i16(nsimd_neon128_vi16 a0);
nsimd_neon128_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_u16_u16(nsimd_neon128_vu16 a0);
nsimd_neon128_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_f16_f16(nsimd_neon128_vf16 a0);
nsimd_neon128_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_i32_i32(nsimd_neon128_vi32 a0);
nsimd_neon128_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_u32_u32(nsimd_neon128_vu32 a0);
nsimd_neon128_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_neon128_f32_f32(nsimd_neon128_vf32 a0);nsimd_avx512_skylake_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_i8_i8(nsimd_avx512_skylake_vi8 a0);
nsimd_avx512_skylake_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_u8_u8(nsimd_avx512_skylake_vu8 a0);
nsimd_avx512_skylake_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_i16_i16(nsimd_avx512_skylake_vi16 a0);
nsimd_avx512_skylake_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_u16_u16(nsimd_avx512_skylake_vu16 a0);
nsimd_avx512_skylake_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_f16_f16(nsimd_avx512_skylake_vf16 a0);
nsimd_avx512_skylake_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_i32_i32(nsimd_avx512_skylake_vi32 a0);
nsimd_avx512_skylake_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_u32_u32(nsimd_avx512_skylake_vu32 a0);
nsimd_avx512_skylake_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_skylake_f32_f32(nsimd_avx512_skylake_vf32 a0);nsimd_aarch64_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_i8_i8(nsimd_aarch64_vi8 a0);
nsimd_aarch64_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_u8_u8(nsimd_aarch64_vu8 a0);
nsimd_aarch64_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_i16_i16(nsimd_aarch64_vi16 a0);
nsimd_aarch64_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_u16_u16(nsimd_aarch64_vu16 a0);
nsimd_aarch64_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_f16_f16(nsimd_aarch64_vf16 a0);
nsimd_aarch64_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_i32_i32(nsimd_aarch64_vi32 a0);
nsimd_aarch64_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_u32_u32(nsimd_aarch64_vu32 a0);
nsimd_aarch64_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_aarch64_f32_f32(nsimd_aarch64_vf32 a0);nsimd_avx512_knl_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_i8_i8(nsimd_avx512_knl_vi8 a0);
nsimd_avx512_knl_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_u8_u8(nsimd_avx512_knl_vu8 a0);
nsimd_avx512_knl_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_i16_i16(nsimd_avx512_knl_vi16 a0);
nsimd_avx512_knl_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_u16_u16(nsimd_avx512_knl_vu16 a0);
nsimd_avx512_knl_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_f16_f16(nsimd_avx512_knl_vf16 a0);
nsimd_avx512_knl_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_i32_i32(nsimd_avx512_knl_vi32 a0);
nsimd_avx512_knl_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_u32_u32(nsimd_avx512_knl_vu32 a0);
nsimd_avx512_knl_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_avx512_knl_f32_f32(nsimd_avx512_knl_vf32 a0);nsimd_sse2_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_i8_i8(nsimd_sse2_vi8 a0);
nsimd_sse2_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_u8_u8(nsimd_sse2_vu8 a0);
nsimd_sse2_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_i16_i16(nsimd_sse2_vi16 a0);
nsimd_sse2_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_u16_u16(nsimd_sse2_vu16 a0);
nsimd_sse2_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_f16_f16(nsimd_sse2_vf16 a0);
nsimd_sse2_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_i32_i32(nsimd_sse2_vi32 a0);
nsimd_sse2_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_u32_u32(nsimd_sse2_vu32 a0);
nsimd_sse2_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sse2_f32_f32(nsimd_sse2_vf32 a0);nsimd_sse42_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_i8_i8(nsimd_sse42_vi8 a0);
nsimd_sse42_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_u8_u8(nsimd_sse42_vu8 a0);
nsimd_sse42_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_i16_i16(nsimd_sse42_vi16 a0);
nsimd_sse42_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_u16_u16(nsimd_sse42_vu16 a0);
nsimd_sse42_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_f16_f16(nsimd_sse42_vf16 a0);
nsimd_sse42_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_i32_i32(nsimd_sse42_vi32 a0);
nsimd_sse42_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_u32_u32(nsimd_sse42_vu32 a0);
nsimd_sse42_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sse42_f32_f32(nsimd_sse42_vf32 a0);nsimd_sve256_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_i8_i8(nsimd_sve256_vi8 a0);
nsimd_sve256_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_u8_u8(nsimd_sve256_vu8 a0);
nsimd_sve256_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_i16_i16(nsimd_sve256_vi16 a0);
nsimd_sve256_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_u16_u16(nsimd_sve256_vu16 a0);
nsimd_sve256_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_f16_f16(nsimd_sve256_vf16 a0);
nsimd_sve256_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_i32_i32(nsimd_sve256_vi32 a0);
nsimd_sve256_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_u32_u32(nsimd_sve256_vu32 a0);
nsimd_sve256_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve256_f32_f32(nsimd_sve256_vf32 a0);nsimd_sve1024_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_i8_i8(nsimd_sve1024_vi8 a0);
nsimd_sve1024_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_u8_u8(nsimd_sve1024_vu8 a0);
nsimd_sve1024_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_i16_i16(nsimd_sve1024_vi16 a0);
nsimd_sve1024_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_u16_u16(nsimd_sve1024_vu16 a0);
nsimd_sve1024_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_f16_f16(nsimd_sve1024_vf16 a0);
nsimd_sve1024_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_i32_i32(nsimd_sve1024_vi32 a0);
nsimd_sve1024_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_u32_u32(nsimd_sve1024_vu32 a0);
nsimd_sve1024_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve1024_f32_f32(nsimd_sve1024_vf32 a0);nsimd_vsx_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_i8_i8(nsimd_vsx_vi8 a0);
nsimd_vsx_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_u8_u8(nsimd_vsx_vu8 a0);
nsimd_vsx_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_i16_i16(nsimd_vsx_vi16 a0);
nsimd_vsx_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_u16_u16(nsimd_vsx_vu16 a0);
nsimd_vsx_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_f16_f16(nsimd_vsx_vf16 a0);
nsimd_vsx_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_i32_i32(nsimd_vsx_vi32 a0);
nsimd_vsx_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_u32_u32(nsimd_vsx_vu32 a0);
nsimd_vsx_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_vsx_f32_f32(nsimd_vsx_vf32 a0);nsimd_sve128_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_i8_i8(nsimd_sve128_vi8 a0);
nsimd_sve128_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_u8_u8(nsimd_sve128_vu8 a0);
nsimd_sve128_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_i16_i16(nsimd_sve128_vi16 a0);
nsimd_sve128_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_u16_u16(nsimd_sve128_vu16 a0);
nsimd_sve128_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_f16_f16(nsimd_sve128_vf16 a0);
nsimd_sve128_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_i32_i32(nsimd_sve128_vi32 a0);
nsimd_sve128_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_u32_u32(nsimd_sve128_vu32 a0);
nsimd_sve128_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_sve128_f32_f32(nsimd_sve128_vf32 a0);nsimd_vmx_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_i8_i8(nsimd_vmx_vi8 a0);
nsimd_vmx_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_u8_u8(nsimd_vmx_vu8 a0);
nsimd_vmx_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_i16_i16(nsimd_vmx_vi16 a0);
nsimd_vmx_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_u16_u16(nsimd_vmx_vu16 a0);
nsimd_vmx_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_f16_f16(nsimd_vmx_vf16 a0);
nsimd_vmx_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_i32_i32(nsimd_vmx_vi32 a0);
nsimd_vmx_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_u32_u32(nsimd_vmx_vu32 a0);
nsimd_vmx_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_vmx_f32_f32(nsimd_vmx_vf32 a0);nsimd_avx_vi8x2 NSIMD_VECTORCALL nsimd_upcvt_avx_i8_i8(nsimd_avx_vi8 a0);
nsimd_avx_vu8x2 NSIMD_VECTORCALL nsimd_upcvt_avx_u8_u8(nsimd_avx_vu8 a0);
nsimd_avx_vi16x2 NSIMD_VECTORCALL nsimd_upcvt_avx_i16_i16(nsimd_avx_vi16 a0);
nsimd_avx_vu16x2 NSIMD_VECTORCALL nsimd_upcvt_avx_u16_u16(nsimd_avx_vu16 a0);
nsimd_avx_vf16x2 NSIMD_VECTORCALL nsimd_upcvt_avx_f16_f16(nsimd_avx_vf16 a0);
nsimd_avx_vi32x2 NSIMD_VECTORCALL nsimd_upcvt_avx_i32_i32(nsimd_avx_vi32 a0);
nsimd_avx_vu32x2 NSIMD_VECTORCALL nsimd_upcvt_avx_u32_u32(nsimd_avx_vu32 a0);
nsimd_avx_vf32x2 NSIMD_VECTORCALL nsimd_upcvt_avx_f32_f32(nsimd_avx_vf32 a0);nsimd_avx2_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vi8 a0, i8, i8, avx2);
nsimd_avx2_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vu8 a0, u8, u8, avx2);
nsimd_avx2_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vi16 a0, i16, i16, avx2);
nsimd_avx2_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vu16 a0, u16, u16, avx2);
nsimd_avx2_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vf16 a0, f16, f16, avx2);
nsimd_avx2_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vi32 a0, i32, i32, avx2);
nsimd_avx2_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vu32 a0, u32, u32, avx2);
nsimd_avx2_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_avx2_vf32 a0, f32, f32, avx2);nsimd_sve512_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vi8 a0, i8, i8, sve512);
nsimd_sve512_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vu8 a0, u8, u8, sve512);
nsimd_sve512_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vi16 a0, i16, i16, sve512);
nsimd_sve512_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vu16 a0, u16, u16, sve512);
nsimd_sve512_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vf16 a0, f16, f16, sve512);
nsimd_sve512_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vi32 a0, i32, i32, sve512);
nsimd_sve512_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vu32 a0, u32, u32, sve512);
nsimd_sve512_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve512_vf32 a0, f32, f32, sve512);nsimd_sve_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vi8 a0, i8, i8, sve);
nsimd_sve_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vu8 a0, u8, u8, sve);
nsimd_sve_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vi16 a0, i16, i16, sve);
nsimd_sve_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vu16 a0, u16, u16, sve);
nsimd_sve_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vf16 a0, f16, f16, sve);
nsimd_sve_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vi32 a0, i32, i32, sve);
nsimd_sve_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vu32 a0, u32, u32, sve);
nsimd_sve_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve_vf32 a0, f32, f32, sve);nsimd_cpu_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vi8 a0, i8, i8, cpu);
nsimd_cpu_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vu8 a0, u8, u8, cpu);
nsimd_cpu_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vi16 a0, i16, i16, cpu);
nsimd_cpu_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vu16 a0, u16, u16, cpu);
nsimd_cpu_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vf16 a0, f16, f16, cpu);
nsimd_cpu_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vi32 a0, i32, i32, cpu);
nsimd_cpu_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vu32 a0, u32, u32, cpu);
nsimd_cpu_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_cpu_vf32 a0, f32, f32, cpu);nsimd_sve2048_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vi8 a0, i8, i8, sve2048);
nsimd_sve2048_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vu8 a0, u8, u8, sve2048);
nsimd_sve2048_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vi16 a0, i16, i16, sve2048);
nsimd_sve2048_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vu16 a0, u16, u16, sve2048);
nsimd_sve2048_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vf16 a0, f16, f16, sve2048);
nsimd_sve2048_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vi32 a0, i32, i32, sve2048);
nsimd_sve2048_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vu32 a0, u32, u32, sve2048);
nsimd_sve2048_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve2048_vf32 a0, f32, f32, sve2048);nsimd_neon128_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vi8 a0, i8, i8, neon128);
nsimd_neon128_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vu8 a0, u8, u8, neon128);
nsimd_neon128_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vi16 a0, i16, i16, neon128);
nsimd_neon128_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vu16 a0, u16, u16, neon128);
nsimd_neon128_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vf16 a0, f16, f16, neon128);
nsimd_neon128_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vi32 a0, i32, i32, neon128);
nsimd_neon128_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vu32 a0, u32, u32, neon128);
nsimd_neon128_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_neon128_vf32 a0, f32, f32, neon128);nsimd_avx512_skylake_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vi8 a0, i8, i8, avx512_skylake);
nsimd_avx512_skylake_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vu8 a0, u8, u8, avx512_skylake);
nsimd_avx512_skylake_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vi16 a0, i16, i16, avx512_skylake);
nsimd_avx512_skylake_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vu16 a0, u16, u16, avx512_skylake);
nsimd_avx512_skylake_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vf16 a0, f16, f16, avx512_skylake);
nsimd_avx512_skylake_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vi32 a0, i32, i32, avx512_skylake);
nsimd_avx512_skylake_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vu32 a0, u32, u32, avx512_skylake);
nsimd_avx512_skylake_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_skylake_vf32 a0, f32, f32, avx512_skylake);nsimd_aarch64_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vi8 a0, i8, i8, aarch64);
nsimd_aarch64_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vu8 a0, u8, u8, aarch64);
nsimd_aarch64_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vi16 a0, i16, i16, aarch64);
nsimd_aarch64_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vu16 a0, u16, u16, aarch64);
nsimd_aarch64_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vf16 a0, f16, f16, aarch64);
nsimd_aarch64_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vi32 a0, i32, i32, aarch64);
nsimd_aarch64_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vu32 a0, u32, u32, aarch64);
nsimd_aarch64_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_aarch64_vf32 a0, f32, f32, aarch64);nsimd_avx512_knl_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vi8 a0, i8, i8, avx512_knl);
nsimd_avx512_knl_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vu8 a0, u8, u8, avx512_knl);
nsimd_avx512_knl_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vi16 a0, i16, i16, avx512_knl);
nsimd_avx512_knl_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vu16 a0, u16, u16, avx512_knl);
nsimd_avx512_knl_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vf16 a0, f16, f16, avx512_knl);
nsimd_avx512_knl_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vi32 a0, i32, i32, avx512_knl);
nsimd_avx512_knl_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vu32 a0, u32, u32, avx512_knl);
nsimd_avx512_knl_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_avx512_knl_vf32 a0, f32, f32, avx512_knl);nsimd_sse2_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vi8 a0, i8, i8, sse2);
nsimd_sse2_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vu8 a0, u8, u8, sse2);
nsimd_sse2_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vi16 a0, i16, i16, sse2);
nsimd_sse2_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vu16 a0, u16, u16, sse2);
nsimd_sse2_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vf16 a0, f16, f16, sse2);
nsimd_sse2_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vi32 a0, i32, i32, sse2);
nsimd_sse2_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vu32 a0, u32, u32, sse2);
nsimd_sse2_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sse2_vf32 a0, f32, f32, sse2);nsimd_sse42_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vi8 a0, i8, i8, sse42);
nsimd_sse42_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vu8 a0, u8, u8, sse42);
nsimd_sse42_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vi16 a0, i16, i16, sse42);
nsimd_sse42_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vu16 a0, u16, u16, sse42);
nsimd_sse42_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vf16 a0, f16, f16, sse42);
nsimd_sse42_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vi32 a0, i32, i32, sse42);
nsimd_sse42_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vu32 a0, u32, u32, sse42);
nsimd_sse42_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sse42_vf32 a0, f32, f32, sse42);nsimd_sve256_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vi8 a0, i8, i8, sve256);
nsimd_sve256_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vu8 a0, u8, u8, sve256);
nsimd_sve256_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vi16 a0, i16, i16, sve256);
nsimd_sve256_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vu16 a0, u16, u16, sve256);
nsimd_sve256_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vf16 a0, f16, f16, sve256);
nsimd_sve256_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vi32 a0, i32, i32, sve256);
nsimd_sve256_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vu32 a0, u32, u32, sve256);
nsimd_sve256_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve256_vf32 a0, f32, f32, sve256);nsimd_sve1024_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vi8 a0, i8, i8, sve1024);
nsimd_sve1024_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vu8 a0, u8, u8, sve1024);
nsimd_sve1024_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vi16 a0, i16, i16, sve1024);
nsimd_sve1024_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vu16 a0, u16, u16, sve1024);
nsimd_sve1024_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vf16 a0, f16, f16, sve1024);
nsimd_sve1024_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vi32 a0, i32, i32, sve1024);
nsimd_sve1024_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vu32 a0, u32, u32, sve1024);
nsimd_sve1024_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve1024_vf32 a0, f32, f32, sve1024);nsimd_vsx_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vi8 a0, i8, i8, vsx);
nsimd_vsx_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vu8 a0, u8, u8, vsx);
nsimd_vsx_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vi16 a0, i16, i16, vsx);
nsimd_vsx_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vu16 a0, u16, u16, vsx);
nsimd_vsx_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vf16 a0, f16, f16, vsx);
nsimd_vsx_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vi32 a0, i32, i32, vsx);
nsimd_vsx_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vu32 a0, u32, u32, vsx);
nsimd_vsx_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_vsx_vf32 a0, f32, f32, vsx);nsimd_sve128_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vi8 a0, i8, i8, sve128);
nsimd_sve128_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vu8 a0, u8, u8, sve128);
nsimd_sve128_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vi16 a0, i16, i16, sve128);
nsimd_sve128_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vu16 a0, u16, u16, sve128);
nsimd_sve128_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vf16 a0, f16, f16, sve128);
nsimd_sve128_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vi32 a0, i32, i32, sve128);
nsimd_sve128_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vu32 a0, u32, u32, sve128);
nsimd_sve128_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_sve128_vf32 a0, f32, f32, sve128);nsimd_vmx_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vi8 a0, i8, i8, vmx);
nsimd_vmx_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vu8 a0, u8, u8, vmx);
nsimd_vmx_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vi16 a0, i16, i16, vmx);
nsimd_vmx_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vu16 a0, u16, u16, vmx);
nsimd_vmx_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vf16 a0, f16, f16, vmx);
nsimd_vmx_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vi32 a0, i32, i32, vmx);
nsimd_vmx_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vu32 a0, u32, u32, vmx);
nsimd_vmx_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_vmx_vf32 a0, f32, f32, vmx);nsimd_avx_vi8x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vi8 a0, i8, i8, avx);
nsimd_avx_vu8x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vu8 a0, u8, u8, avx);
nsimd_avx_vi16x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vi16 a0, i16, i16, avx);
nsimd_avx_vu16x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vu16 a0, u16, u16, avx);
nsimd_avx_vf16x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vf16 a0, f16, f16, avx);
nsimd_avx_vi32x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vi32 a0, i32, i32, avx);
nsimd_avx_vu32x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vu32 a0, u32, u32, avx);
nsimd_avx_vf32x2 NSIMD_VECTORCALL upcvt(nsimd_avx_vf32 a0, f32, f32, avx);